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DATA SHEET
MOS INTEGRATED CIRCUIT
PD789304, 789306, 789314, 789316
8-BIT SINGLE-CHIP MICROCONTROLLER
The PD789304, 789306, 789314, and 789316 belong to the PD789306, 789316 Subseries (for LCD drivers) in the 78K/0S Series. Flash memory versions (PD78F9306, 78F9316) that can be operated using the same power supply voltage as mask ROM versions are available, along with various development tools. Detailed function descriptions are provided in the following user's manuals. Be sure to read them before designing. PD789306, 789316 Subseries User's Manual: U14800E 78K/0S Series User's Manual Instructions: U11047E
FEATURES
* ROM and RAM capacities
Item Part Number Program Memory (ROM) Data Memory Internal High-Speed RAM 8 KB 16 KB 512 bytes LCD Display RAM 24 bytes
PD789304, 789314 PD789306, 789316
*
Main system clock Ceramic/crystal oscillation: PD789304, 789306 RC oscillation:
PD789314, 789316
* *
I/O ports: 23 Serial interface: 2 channels Switchable between 3-wire serial I/O mode and UART mode: 1 channel 3-wire serial I/O mode: 1 channel
* * *
LCD controller/driver Segment signals: 24, common signals: 4 Timer: 5 channels Power supply voltage: VDD = 1.8 to 5.5 V
APPLICATIONS
Remote control devices, healthcare equipment, etc.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. U14384EJ1V0DS00 (1st edition) Date Published March 2001 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
1999 1996, 1999
PD789304, 789306, 789314, 789316
ORDERING INFORMATION
Part Number Package 64-pin plastic QFP (14 x 14) 64-pin plastic TQFP (12 x 12) 64-pin plastic QFP (14 x 14) 64-pin plastic TQFP (12 x 12) 64-pin plastic QFP (14 x 14) 64-pin plastic TQFP (12 x 12) 64-pin plastic QFP (14 x 14) 64-pin plastic TQFP (12 x 12)
PD789304GC-xxx-AB8 PD789304GK-xxx-9ET PD789306GC-xxx-AB8 PD789306GK-xxx-9ET PD789314GC-xxx-AB8 PD789314GK-xxx-9ET PD789316GC-xxx-AB8 PD789316GK-xxx-9ET
Remark
xxx indicates ROM code suffix.
2
Data Sheet U14384EJ1V0DS
PD789304, 789306, 789314, 789316
78K/0S SERIES LINEUP The products in the 78K/0S Series are listed below. The names enclosed in boxes are subseries names.
Products in mass production Products under development Y subseries products support SMB. Small-scale package, general-purpose applications 44-pin 42-/44-pin 30-pin 28-pin
PD789046 PD789026 PD789074 PD789014
PD789074 with added subsystem clock PD789014 with enhanced timer and increased ROM, RAM capacity PD789026 with enhanced timer
On-chip UART and capable of low voltage (1.8 V) operation
Small-scale package, general-purpose applications and A/D converter 44-pin 44-pin 30-pin 30-pin 30-pin 30-pin 30-pin 30-pin
PD789177 PD789167 PD789156 PD789146 PD789134A PD789124A PD789114A PD789104A
Inverter control
PD789177Y PD789167Y
PD789167 with enhanced A/D converter PD789104A with enhanced timer PD789146 with enhanced A/D converter PD789104A with added EEPROMTM PD789124A with enhanced A/D converter RC oscillation version of the PD789104A PD789104A with enhanced A/D converter PD789026 with added A/D converter and multiplier
44-pin
PD789842
On-chip inverter controller and UART
VFD drive 78K/0S Series 52-pin
PD789871
Total display outputs: 25
LCD drive 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin
PD789488 PD789417A PD789407A PD789456 PD789446 PD789436 PD789426 PD789316 PD789306
Dot LCD drive
A/D converter and on-chip voltage booster type LCD (28 x 4) PD789407A with enhanced A/D converter A/D converter and resistance division type LCD (28 x 4) PD789446 with enhanced A/D converter A/D converter and on-chip voltage booster type LCD (15 x 4) PD789426 with enhanced A/D A/D converter and on-chip voltage booster type LCD (5 x 4) RC oscillation version of the PD789306 On-chip voltage booster type LCD (24 x 4)
144-pin 88-pin
PD789835 PD789830
Segment/common outputs: 96 Segments: 40, commons: 16
ASSP 80-pin 52-pin 52-pin 64-pin 44-pin 44-pin 20-pin 20-pin
PD789477 PD789467 PD789327 PD789803 PD789800 PD789840 PD789861 PD789860
PD789488 with added remote control receiver and resistance division type LCD For remote controller, with A/D converter and on-chip voltage booster type LCD For remote controller, with SIO and resistance division type LCD
For PC keyboard, on-chip USB HUB function For PC keyboard, on-chip USB function For keypad, on-chip POC RC oscillation version of the PD789860 For keyless entry, on-chip POC and key return circuit
Data Sheet U14384EJ1V0DS
3
PD789304, 789306, 789314, 789316
The major functional differences among the subseries are listed below.
Function ROM Capacity Subseries Name Small-scale package, generalpurpose applications Smallscale package, generalpurpose applications and A/D converter 8-Bit 16-Bit Watch WDT 8-Bit 10-Bit A/D A/D - - Serial Interface 1 ch (UART: 1 ch) VDD I/O MIN. Value 34 1.8 V Remarks
PD789046 PD789026 PD789074 PD789014 PD789177 PD789167 PD789156 PD789146 PD789134A PD789124A PD789114A PD789104A
16 K 4 K to 16 K 2 K to 8 K 2 K to 4 K 16 K to 24 K
1 ch
1 ch
1 ch -
1 ch
-
24 2 ch 3 ch - 1 ch 1 ch - - 8 ch - 4 ch - 4 ch - 4 ch Note - 1 ch 8 ch - 4 ch - 4 ch - 4 ch - - - 8 ch 7 ch 7 ch 2 ch - 6 ch - 6 ch - 6 ch - 6 ch - 2 ch (UART: 1 ch) 23 RC-oscillation version - 40 1 ch (UART: 1 ch) 1 ch 2 ch (UART: 1 ch) 1 ch (UART: 1 ch) 30 4.0 V 33 2.7 V 45 1.8 V 43 - - - 1 ch (UART: 1 ch) 22 31 -
8 K to 16 K
1 ch
20
On-chip EEPROM RC-oscillation version -
2 K to 8 K
Inverter control VFD drive LCD drive
PD789842 PD789871 PD789488 PD789417A PD789407A PD789456 PD789446 PD789436 PD789426 PD789316 PD789306
8 K to 16 K 4 K to 8 K 32 K 12 K to 24 K 12 K to 16 K
3 ch 3 ch 3 ch
1 ch 1 ch 1 ch
1 ch 1 ch 1 ch
8 ch - -
30
8 K to 16 K
-
Dot LCD drive
PD789835 PD789830
24 K to 60 K 24 K 24 K 4 K to 24 K
6 ch 1 ch 3 ch 2 ch
- 1 ch 1 ch -
1 ch
1 ch
3 ch -
-
1 ch (UART: 1 ch)
28 1.8 V 30 2.7 V
-
ASSP
PD789477 PD789467 PD789327 PD789803 PD789800 PD789840 PD789861
1 ch
1 ch
8 ch 1 ch -
-
2 ch (UART: 1 ch) - 1 ch 2 ch (USB: 1 ch)
45 1.8 V On-chip LCD 18 21 41 3.6 V 31 4.0 V 29 2.8 V -
8 K to 16 K 8K
-
4 ch 4K -
1 ch -
14 1.8 V RC-oscillation version, on-chip EEPROM On-chip EEPROM
PD789860
Note 10-bit timer: 1 channel
4
Data Sheet U14384EJ1V0DS
PD789304, 789306, 789314, 789316
OVERVIEW OF FUNCTIONS
Item Internal memory ROM High-speed RAM LCD display RAM Main system clock (oscillation frequency) Subsystem clock (oscillation frequency) Minimum instruction execution time
PD789304
8 KB 512 bytes 24 bytes
PD789306
16 KB
PD789314
8 KB
PD789316
16 KB
Ceramic/crystal oscillation (1.0 to 5.0 MHz) Crystal oscillation (32.768 kHz) 0.4 s/1.6 s (@ 5.0 MHz operation with main system clock)
RC oscillation (2.0 to 4.0 MHz)
0.5 s/2.0 s (@ 4.0 MHz operation with main system clock)
122 s (@ 32.768 kHz operation with subsystem clock) General-purpose registers Instruction set I/O ports 8 bits x 8 registers * 16-bit operation * Bit manipulation (set, reset, test) Total: * CMOS I/O: * N-ch open drain: * * * * 16-bit timer: 8-bit timer/event counter: Watch timer: Watchdog timer: 23 19 4 1 channel 2 channels 1 channel 1 channel
Timers
Serial interface LCD controller/driver Vectored interrupt Maskable sources Non-maskable Power supply voltage Operating ambient temperature Package
* Switchable between 3-wire serial I/O mode and UART mode: 1 channel * 3-wire serial I/O mode: 1 channel * Segment signal outputs: 24 (Max.) * Common signal outputs: 4 (Max.) Internal: 9, External: 5 Internal: 1 VDD = 1.8 to 5.5 V TA = -40 to +85C * 64-pin plastic QFP (14 x 14) * 64-pin plastic TQFP (12 x 12)
Data Sheet U14384EJ1V0DS
5
PD789304, 789306, 789314, 789316
CONTENTS
1. 2. 3.
PIN CONFIGURATION (TOP VIEW) ..................................................................................................................... 7 BLOCK DIAGRAM ................................................................................................................................................ 9 PIN FUNCTIONS ................................................................................................................................................. 10 3.1 3.2 3.3 Port Pins ................................................................................................................................................... 10 Non-Port Pins ........................................................................................................................................... 11 Pin I/O Circuits and Recommended Connection of Unused Pins ............................................................. 12
4. 5.
MEMORY SPACE................................................................................................................................................ 14 PERIPHERAL HARDWARE FUNCTIONS .......................................................................................................... 15 5.1 5.2 5.3 5.4 5.5 Ports ......................................................................................................................................................... 15 Clock Generator........................................................................................................................................ 16 Timer......................................................................................................................................................... 17 Serial Interface.......................................................................................................................................... 22 LCD Controller/Driver................................................................................................................................ 25
6. 7. 8. 9.
INTERRUPT FUNCTIONS................................................................................................................................... 27 STANDBY FUNCTION ........................................................................................................................................ 29 RESET FUNCTION.............................................................................................................................................. 29 MASK OPTIONS ................................................................................................................................................. 29
10. OVERVIEW OF INSTRUCTION SET .................................................................................................................. 30 10.1 10.2 Conventions.............................................................................................................................................. 30 List of Operations...................................................................................................................................... 32
11. ELECTRICAL SPECIFICATIONS ....................................................................................................................... 37 12. CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER (REFERENCE VALUES)............................ 54 13. PACKAGE DRAWINGS ...................................................................................................................................... 56 14. RECOMMENDED SOLDERING CONDITIONS................................................................................................... 58 APPENDIX A. DEVELOPMENT TOOLS ................................................................................................................. 59 APPENDIX B. RELATED DOCUMENTS................................................................................................................. 61
6
Data Sheet U14384EJ1V0DS
PD789304, 789306, 789314, 789316
1. PIN CONFIGURATION (TOP VIEW)
64-pin plastic QFP (14 x 14) 64-pin plastic TQFP (12 x 12)
PD789304GC-xxx-AB8 PD789306GC-xxx-AB8 PD789314GC-xxx-AB8 PD789316GC-xxx-AB8
PD789304GK-xxx-9ET PD789306GK-xxx-9ET PD789314GK-xxx-9ET PD789316GK-xxx-9ET
P50 P51 P52 P53 IC XT1 XT2 VDD VSS X1 (CL1) X2 (CL2) RESET P00/KR0 P01/KR1 P02/KR2 P03/KR3
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 8 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
P20/SCK10 P21/SO10 P22/SI10 P23/SCK20/ASCK20 P24/SO20/TxD20 P25/SI20/RxD20 P26/TO20 P30/INTP0/CPT20 P31/INTP1/TO30/TMI40 P32/INTP2/TO40 P33/INTP3 P10 P11 P12 P13 S23
S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7
Caution Remark
Connect the IC (Internally Connected) pin directly to the VSS pin. Pin names enclosed in parentheses are when using the PD789314, 789316.
CAPH CAPL VLC0 VLC1 VLC2 COM0 COM1 COM2 COM3 S0 S1 S2 S3 S4 S5 S6
Data Sheet U14384EJ1V0DS
7
PD789304, 789306, 789314, 789316
ASCK20: CAPH, CAPL: CL1, CL2: COM0 to COM3: CPT20: IC: INTP0 to INTP3: KR0 to KR3: P00 to P03: P10 to P13: P20 to P26: P30 to P33: P50 to P53: Asynchronous serial input LCD power supply capacitance control RC oscillator Common output Capture trigger input Internally connected External interrupt input Key return Port 0 Port 1 Port 2 Port 3 Port 5 RESET: RxD20: S0 to S23: SCK10, SCK20: SI10, SI20: SO10, SO20: TMI40: TO20, TO30, TO40: TxD20: VDD: VLC0 to VLC2: VSS: X1, X2: XT1, XT2: Reset Receive data Segment output Serial clock Serial input Serial output Timer input Timer output Transmit data Power supply LCD power supply Ground Crystal/ceramic oscillator Crystal oscillator
8
Data Sheet U14384EJ1V0DS
PD789304, 789306, 789314, 789316
2. BLOCK DIAGRAM
TO30/TMI40/P31 TO40/P32 TMI40/TO30/P31
Cascaded 16-bit timer/event counter
8-bit timer 30 8-bit timer/event counter 40
Port 0
P00 to P03
Port 1
P10 to P13
TO20/P26 CPT20/P30
16-bit timer 20
Port 2 78K/0S CPU core
P20 to P26
ROM
Watch timer
Port 3
P30 to P33
Port 5 Watchdog timer
P50 to P53
SCK10/P20 SO10/P21 SI10/P22
Serial interface 10
RAM
RAM space for LCD data
System control
RESET X1 (CL1) X2 (CL2) XT1 XT2 INTP0/P30 INTP1/P31
SCK20/ASCK20/P23 SO20/TxD20/P24 SI20/RxD20/P25
Serial interface 20
Interrupt control S0 to S23 COM0 to COM3 VLC0 to VLC2 CAPH CAPL LCD controller driver
INTP2/P32 INTP3/P33 KR0/P00 to KR3/P03
VDD
VSS
IC
Remark
Pin names enclosed in parentheses are when using the PD789314, 789316.
Data Sheet U14384EJ1V0DS
9
PD789304, 789306, 789314, 789316
3. PIN FUNCTIONS
3.1 Port Pins
Pin Name P00 to P03 I/O I/O Function Port 0. 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified in port units by software. Port 1. 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified in port units by software. Port 2. 7-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified in 1-bit units by software. After Reset Input Alternate Function KR0 to KR3
P10 to P13
I/O
Input
-
P20 P21 P22 P23 P24 P25 P26 P30 P31 P32 P33 P50 to P53
I/O
Input
SCK10 SO10 SI10 SCK20/ASCK20 SO20/TxD20 SI20/RxD20 TO20
I/O
Port 3. 4-bit I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified in 1-bit units by software. Port 5. 4-bit I/O port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified in bit units by the mask option.
Input
INTP0/CPT20 INTP1/TO30/TMI40 INTP2/TO40 INTP3
I/O
Input
-
10
Data Sheet U14384EJ1V0DS
PD789304, 789306, 789314, 789316
3.2 Non-Port Pins
Pin Name INTP0 INTP1 INTP2 INTP3 KR0 to KR3 SCK10 SCK20 SI10 SI20 SO10 SO20 ASCK20 RxD20 TxD20 TO20 CPT20 TO30 TO40 TMI40 S0 to S23 Input Input Output Output Input Output Output Input Output Output Input Input I/O Key return signal detection Serial clock input/output for serial interface (SIO10) Serial clock input/output for serial interface (SIO20) Serial data input for SIO10 serial interface Serial data input for SIO20 serial interface Serial data output for SIO10 serial interface Serial data output for SIO20 serial interface Serial clock input for asynchronous serial interface Serial data input for asynchronous serial interface Serial data output for asynchronous serial interface 16-bit timer (TM20) output Capture edge input 8-bit timer (TM30) output 8-bit timer (TM40) output External count clock input to 8-bit timer (TM40) Segment signal output for LCD controller/driver Common signal output for LCD controller/driver LCD drive voltage Connection pin for LCD driver's capacitor Input Input Input Input Input Input Input Input Output Output - - - Connecting crystal resonator for main system clock oscillation - - Connections to resistor (R) and capacitor (C) for main system clock oscillation Connecting crystal resonator for subsystem clock oscillation - - - - System reset input Positive power supply Ground potential Internally connected. Connect directly to VSS. Input - - - Input Input Input Input I/O Input Function External interrupt input for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified After Reset Input Alternate Function P30/CPT20 P31/TO30/TMI40 P32/TO40 P33 P00 to P03 P20 P23/ASCK20 P22 P25/RxD20 P21 P24/TxD20 P23/SCK20 P25/SI20 P24/SO20 P26 P30/INTP0 P31/INTP1/TMI40 P32/INTP2 P31/INTP1/TO30 - - - - - - - - - - - - - - -
COM0 to COM3 Output VLC0 to VLC2 CAPH CAPL X1 X2
Note 1 Note 1 Note 2 Note 2
- - - Input - Input - Input - Input - - -
CL1 CL2 XT1 XT2
RESET VDD VSS IC
Notes 1. 2.
PD789304, 789306 only PD789314, 789316 only
Data Sheet U14384EJ1V0DS
11
PD789304, 789306, 789314, 789316
3.3 Pin I/O Circuits and Recommended Connection of Unused Pins The I/O circuit type of each pin and recommended connection of unused pins are shown in Table 3-1. For the I/O circuit configuration of each type, refer to Figure 3-1. Table 3-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins
Pin Name I/O Circuit Type 8-A 5-A 8-A I/O I/O Recommended Connection of Unused Pins
P00/KR0 to P03/KR3 P10 to P13 P20/SCK10 P21/SO10 P22/SI10 P23/SCK20/ASCK20 P24/SO20/TxD20 P25/SI20/RxD20 P26/TO20 P30/INTP0/CPT20 P31/INTP1/TO30/ TMI40 P32/INTP2/TO40 P33/INTP3 P50 to P53 S0 to S23 COM0 to COM3 VLC0 to VLC2 CAPH, CAPL XT1 XT2 RESET IC
Input: Independently connect to VDD or VSS via a resistor. Output: Leave open.
Input: Independently connect to VSS via a resistor. Output: Leave open.
13-W 17 18 - - - Input - 2 - Input - - Output
Input: Independently connect to VDD via a resistor. Output: Leave open. Leave open.
Connect to VSS. Leave open. - Directly connect to VSS.
12
Data Sheet U14384EJ1V0DS
PD789304, 789306, 789314, 789316
Figure 3-1. Pin I/O Circuits Type 2 Type 13-W
VDD Pull-up resistor (mask option)
IN
IN/OUT Output data Output disable N-ch
Schmitt-triggered input with hysteresis characteristics
VSS Input enable Middle-voltage input buffer
Type 5-A
VDD
Type 17
VLC0
Pull-up enable VDD Data P-ch
P-ch
P-ch
VLC1
P-ch N-ch P-ch
IN/OUT Output disable N-ch VSS
SEG data
N-ch P-ch N-ch N-ch
OUT
VLC2
Input enable
Type 8-A
VDD
Type 18
VLC0
P-ch P-ch N-ch P-ch N-ch
Pull-up enable VDD Data P-ch
P-ch
VLC1
IN/OUT Output disable N-ch VSS
COM data VLC2
N-ch P-ch N-ch
OUT
N-ch P-ch
Data Sheet U14384EJ1V0DS
13
PD789304, 789306, 789314, 789316
4. MEMORY SPACE
Figure 4-1 shows the memory map of the PD789304, 789306, 789314, and 789316. Figure 4-1. Memory Map
FFFFH Special function registers (SFR) 256 x 8 bits FF00H FEFFH Internal high-speed RAM 512 x 8 bits FD00H FCFFH Reserved FA18H FA17H Data memory space LCD display RAM 24 x 4 bits FA00H F9FFH nnnnH+1 nnnnH Reserved nnnnH
Program area
Program memory space
Internal ROMNote
0080H 007FH CALLT table area 0040H 003FH Program area 0022H 0021H
0000H
0000H
Vector table area
Note The internal ROM capacity depends on the product (see the following table).
Part Number Last Address of Internal ROM nnnnH 1FFFH 3FFFH
PD789304, 789314 PD789306, 789316
14
Data Sheet U14384EJ1V0DS
PD789304, 789306, 789314, 789316
5. PERIPHERAL HARDWARE FUNCTIONS
5.1 Ports The I/O ports are listed below. * CMOS I/O: * N-ch open-drain I/O: 19 4 Table 5-1. Port Functions
Port Name Port 0 Port 1 Port 2 Port 3 Port 5 Pin Name P00 to P03 P10 to P13 P20 to P26 P30 to P33 P50 to P53 Function I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by software. I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by software. I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by software. I/O port. Input/output can be specified in 1-bit units. When used as an input port, an on-chip pull-up resistor can be specified by software. I/O port. Input/output can be specified in 1-bit units. An on-chip pull-up resistor can be specified by the mask option.
Data Sheet U14384EJ1V0DS
15
PD789304, 789306, 789314, 789316
5.2 Clock Generator The specifications of the main system clock generator differ depending on the product as shown below. (1) Main system clock generator * Ceramic/crystal oscillation: PD789304, 789306 This generator's oscillation frequency range is 1.0 to 5.0 MHz. The minimum instruction execution time can be changed from 0.4 to 1.6 s (@ 5.0 MHz operation). * RC oscillation: PD789314, 789316 This generator's oscillation frequency range is 2.0 to 4.0 MHz. The minimum instruction execution time can be changed from 0.5 to 2.0 s (@ 4.0 MHz operation). (2) Subsystem clock generator (crystal oscillation) This generator's oscillation frequency is 32.768 kHz. The minimum instruction execution time is 122 s (@ 32.768 kHz operation). Figure 5-1. Block Diagram of Clock Generator
Internal bus
FRC SCC
Sub oscillation mode register (SCKM)
XT1 XT2
fXT Subsystem clock oscillator Prescaler 1/2
Watch timer LCD controller/driver
X1 (CL1) X2 (CL2)
Main system clock oscillator
Prescaler fX (fcc) fX 22 ( fCC) 22
fXT 2
Clock to peripheral hardware
Selector
Standby controller
Wait controller
CPU clock (fCPU)
STOP
MCC PCC1 Processor clock control register (PCC)
CLS CSS0 Subsystem clock control register (CSS)
Internal bus
Remark
Pins names enclosed in parentheses are when using the RC oscillation (PD789314, 789316).
Data Sheet U14384EJ1V0DS
16
PD789304, 789306, 789314, 789316
5.3 Timer Five timer channels are incorporated. * 16-bit timer (TM20): * 8-bit timer (TM30, TM40): * Watch timer (WT): * Watchdog timer (WTM): 1 channel 2 channels 1 channel 1 channel Table 5-2. Timer Operation
TM20 Operation Interval time mode External event counter Function Timer output Square wave output Interrupt request 1 channel - 1 output - 1 TM30 1 channel 1 channel 1 output 1 output 1 TM40 1 channel 1 channel 1 output 1 output 1 WT 1 channel - - - 1 WTM 1 channel - - - 1
Figure 5-2. Block Diagram of 16-Bit Timer (TM20)
Internal bus 16-bit timer mode control register 20 (TMC20)
TOF20 CPT201 CPT200 TOC20 TCL201 TCL200 TOE20
P26 output latch
PM26
TO20/P26 16-bit compare register 20 (CR20) Match
Selector
F/F
TOD20
16-bit timer mode control register 20 (TMC20)
fCLK fCLK/22 fCLK/25 fCLK/27 CPT20/P30 /INTP0
INTTM20
OVF 16-bit timer counter 20 (TM20)
Edge detector
16-bit capture register 20 (TCP20)
16-bit counter read buffer
Internal bus
Remark
fCLK: fX or fCC
Data Sheet U14384EJ1V0DS
17
Selector
Carrier clock (during carrier generator mode) or timer 40 output signal (during mode other than carrier generator mode) (from Figure 5-4 (C))
Selector
18
Bit 7 of TM40 (from Figure 5-4 (A))
Data Sheet U14384EJ1V0DS
Figure 5-3. Block Diagram of Timer 30 (TM30)
Internal bus 8-bit timer mode control register 30 (TMC30) TCE30 TCL301 TCL300 TMD300 TOE30
P30 output latch
PM30
Decoder Selector
8-bit compare register 30 (CR30) Match TO30/P31/ INTP1/TMI40
fCLK/24 fCLK/28 Timer 40 interrupt request signal (from Figure 5-4 (B))
8-bit timer counter 30 (TM30) Clear
OVF
PD789304, 789306, 789314, 789316
Internal reset signal
From Figure 5-4 (D) Count operation start signal (during cascade connection mode)
Selector Cascade connection mode INTTM30
From Figure 5-4 (E) Timer 40 match signal (during cascade connection mode) To Figure 5-4 (G) Timer 30 match signal (during carrier generator mode)
To Figure 5-4 (F) Timer 30 match signal (during cascade connection mode)
Remark
fCLK: fX or fCC
Figure 5-4. Block Diagram of Timer 40 (TM40)
Internal bus 8-bit timer mode control register 40 (TMC40) TCE40 TCL402 TCL401 TCL400 TMD401 TMD400 TOE40
8-bit compare register H40 (CRH40) 8-bit compare register 40 (CR40)
Carrier generator output control register 40 (TCA40) RMC40 NRZB40 NRZ40
Decoder Selector
From Figure 5-3 (G) Timer counter match signal from timer 30 (during carrier generator mode)
Match fCLK/23 fCLK/27
Selector
F/F
Output control circuitNote
TO40/P32/INTP2 To Figure 5-3 (C) Carrier clock (during carrier generator mode) or timer 40 output signal (during mode other than carrier generator mode)
Data Sheet U14384EJ1V0DS
8-bit timer counter 40 (TM40) Clear Carrier generator mode PWM mode Reset Cascade connection mode OVF
PD789304, 789306, 789314, 789316
TMI40/P31/ INTP1/TO30
Prescaler
TMI/2 TMI/22 TMI/23
To Figure 5-3 (A) Bit 7 of TM40 (during cascade connection mode)
Internal reset signal To Figure 5-3 (D) Count operation start signal to timer 30 (during cascade connection mode) To Figure 5-3 (E) TM40 timer counter match signal (during cascade connection mode) INTTM40 To Figure 5-3 (B) Timer 40 interrupt request signal count clock input signal to TM30
From Figure 5-3 (F) TM30 match signal (during cascade connection mode)
Note For details, see Figure 5-5. Remark fCLK: fX or fCC
19
PD789304, 789306, 789314, 789316
Figure 5-5. Block Diagram of Output Controller (Timer 40)
TOE40 RMC40 NRZ40 P32 output latch
PM32
Selector
F/F
TO40/P32/ INTP2 Carrier clock (during carrier generator mode) or timer 40 output signal (during mode other than carrier generator mode)
Carrier generator mode
Figure 5-6. Block Diagram of Watch Timer (WT)
Clear
Selector
fCLK/27 fXT
fW fW 24
9-bit prescaler fW 25 fW 26 fW 27 fW 28 fW 29
5-bit counter Clear
INTWT
Selector
INTWTI
WTM7 WTM6 WTM5 WTM4 WTM1 WTM0 Watch timer mode control register (WTM) Internal bus
Remark
fCLK: fX or fCC
20
Data Sheet U14384EJ1V0DS
PD789304, 789306, 789314, 789316
Figure 5-7. Block Diagram of Watchdog Timer (WTM)
Internal bus
fCLK 24 fCLK 26
Prescaler fCLK 28 fCLK 210
WDTMK
WDTIF 7-bit counter Clear 3
Controller
Selector
INTWDT maskable interrupt request RESET INTWDT non-maskable interrupt request
WDCS2 WDCS1 WDCS0 Watchdog timer clock select register (WDCS)
RUN WDTM4 WDTM3 Watchdog timer mode register (WDTM) Internal bus
Remark
fCLK: fX or fCC
Data Sheet U14384EJ1V0DS
21
Selector
Selector
22
Figure 5-8. Block Diagram of Serial Interface 10
Internal bus Serial operation mode register 10 (CSIM10) CSIE10 TPS101 TPS100 DIR10 CSCK10
5.4 Serial Interface
* Operation stop mode
5.4.1 Serial interface 10 (SIO10)
* 3-wire serial I/O mode
SI10/P22
Serial shift register 10 (SIO10)
SO10/P21
PM21
Serial interface 10 (SIO10) has the following two types of modes.
Data Sheet U14384EJ1V0DS
Serial clock counter
Interrupt request generator
INTCSI10
PM20 Clock controller F/F
SCK10/P20
fCLK/22 fCLK/23 fCLK/24 fCLK/25
TPS101 TPS100
PD789304, 789306, 789314, 789316
Remark
fCLK: fX or fCC
Figure 5-9. Block Diagram of Serial Interface 20
Internal bus Asynchronous serial interface status register 20 (ASIS20) Receive buffer register 20 (RXB20/SIO20) PE20 FE20 OVE20 Direction controller TXE20 RXE20 PS201 PS200 CL20 Asynchronous serial interface mode register 20 (ASIM20) SL20
5.4.2 Serial interface 20 (SIO20)
Direction controller
Transmit shift register 20 (TXS20/SIO20)
* Operation stop mode * Asynchronous serial interface (UART) mode * 3-wire serial I/O mode
RxD20/SI20/ P25
Receive shift register 20 (RXS20)
TxD20/SO20/ P24
PM24 Reception controller INTSR20/INTCSI20 Transmission controller SCK20 output controller INTST20
Serial interface 20 (SIO20) has the following three types of modes.
Data Sheet U14384EJ1V0DS
CSIE20 TXE20 RXE20 CSIE20 DIR20 CSCK20 Serial interface mode register 20 (CSIM20) Internal bus
PM23
ASCK20/SCK20/ P23 Baud rate generator
Note
fX/2 to fX/28 4 CSCK20
TPS203 TPS202 TPS201 TPS200 Baud rate generator control register 20 (BRGC20)
PD789304, 789306, 789314, 789316
Note See Figure 5-10 for the configuration of the baud rate generator.
23
Selector
Receive clock counter
Selector
Receive shift clock
1/2
Selector
24
Figure 5-10. Block Diagram of Baud Rate Generator 20
Clock for receive detection Transmit shift clock Transmit clock counter fXX/2 fXX/22 fXX/23 fXX/24 fXX/25 fXX/26 fXX/27 fXX/28 1/2
Data Sheet U14384EJ1V0DS
PD789304, 789306, 789314, 789316
TXE20 RXE20 CSIE20 Receive detection 4
SCK20/ASCK20/P20
TPS203 TPS202 TPS201 TPS200 Baud rate generator control register 20 (BRGC20) Internal bus
PD789304, 789306, 789314, 789316
5.5 LCD Controller/Driver The LCD controller/driver has the following functions. (1) Enables automatic output of segment signals and common signals by automatically reading from display data memory. (2) Two types of display modes can be selected: * 1/3 duty (1/3 bias) * 1/4 duty (1/3 bias) (3) Any of four frame frequency settings can be selected for each display mode. (4) There are up to 24 segment signal outputs (S0 to S23) and four common signal outputs (COM0 to COM3). (5) Operation using the subsystem clock is also supported.
Data Sheet U14384EJ1V0DS
25
Selector
26
Figure 5-11. Block Diagram of LCD Controller/Driver
LCD clock control register 0 (LCDC0)
LCDC03 LCDC02 LCDC01 LCDC00
Internal bus LCD voltage amplifier control register 0 (LCDVA0) FA00H LCDON0 VAON0 LIPS0 LCDM02 LCDM01 LCDM00 GAIN 76543210 LCD display mode register 0 (LCDM0) 3
Display data memory ********** FA17H 76543210
2
2
fCLK/25 fCLK/26 fCLK/27 fXT
Prescaler fLCD 26 fLCD 27 fLCD 28 fLCD 29 LCD fLCD clock selector Voltage amplifier circuit 3210 Selector LCDON0 LCDON0 3210 Selector
Data Sheet U14384EJ1V0DS
Timing controller
PD789304, 789306, 789314, 789316
LCD drive voltage controller
Common driver
Segment driver
Segment driver
********** CAPH CAPL VLC2 VLC1 VLC0 COM0 COM1 COM2 COM3 S0 S23
Remark
fCLK: fX or fCC
PD789304, 789306, 789314, 789316
6. INTERRUPT FUNCTIONS
A total of 15 interrupt sources divided into the following two types are provided. * Non-maskable: * Maskable: 1 14 Table 6-1. Interrupt Source List
Interrupt Type Priority
Note 1
Interrupt Source
Internal/ External
Vector Table Address
Name Nonmaskable Maskable - 0 1 2 3 4 5 INTWDT INTWDT INTP0 INTP1 INTP2 INTP3 INTSR20 INTCSI20 6 7 8 9 10 11 12 13 INTCSI10 INTST20 INTWTI INTTM20 INTTM30 INTTM40 INTWT INTKR00
Trigger Watchdog timer overflow (with watchdog timer mode 1 selected) Watchdog timer overflow (with interval timer mode selected) Pin input edge detection External 0006H 0008H 000AH 000CH End of serial interface 20 UART reception End of serial interface 20 3-wire SIO transfer reception End of serial interface 10 3-wire SIO transfer reception End of serial interface 20 UART transmission Watch timer interval timer interrupt Generation of match signal of 16-bit timer 20 Generation of match signal of 8-bit timer 30 Generation of match signal of 8-bit timer/event counter 40 Watch timer interrupt Key return signal detection External 0010H 0012H 0014H 0016H 0018H 001AH 001EH 0020H Internal 000EH Internal 0004H
Basic Configuration Note 2 Type (A) (B) (C)
(B)
(C)
Notes 1. 2. Remark
Default priority is the priority order when several maskable interrupt requests are generated at the same time. 0 is the highest order and 13 is the lowest order. Basic configuration types (A) to (C) correspond to (A) to (C) in Figure 6-1. Two watchdog timer interrupt sources (INTWDT): a non-maskable interrupt and a maskable interrupt (internal), are available, either of which can be selected.
Data Sheet U14384EJ1V0DS
27
PD789304, 789306, 789314, 789316
Figure 6-1. Basic Configuration of Interrupt Function (A) Internal non-maskable interrupt
Internal bus
Interrupt request
Vector table address generator
Standby release signal
(B) Internal maskable interrupt
Internal bus
MK
IE
Interrupt request
IF
Vector table address generator
Standby release signal
(C) External maskable interrupt
Internal bus
INTM0, INTM1, KRM00
MK
IE
Interrupt request
Edge detector
IF
Vector table address generator
Standby release signal
INTM0: External interrupt mode register 0 INTM1: External interrupt mode register 1 KRM00: Key return mode register 00 IF: IE: MK: Interrupt request flag Interrupt enable flag Interrupt mask flag
28
Data Sheet U14384EJ1V0DS
PD789304, 789306, 789314, 789316
7. STANDBY FUNCTION
The following two standby modes are available for further reduction of system current consumption. * HALT mode: In this mode, the CPU operation clock is stopped. The average current consumption can be reduced by intermittent operation by combining this mode with the normal operation. * STOP mode: In this mode, oscillation of the main system clock is stopped. All operations performed on the main system clock are suspended resulting in extremely small power consumption. Figure 7-1. Standby Function
System clock operation STOP instruction Interrupt request HALT instruction
Interrupt request
(
8. RESET FUNCTION
STOP mode Main system clock oscillation stopped
(
(
HALT mode Clock supply to CPU halted, oscillation maintained
(
The following two reset methods are available. * External reset by RESET pin * Internal reset by watchdog timer program loop time detection
9. MASK OPTIONS
The PD789304, 789306, 789314, and 789316 have the following mask options. * Mask options for P50 to P53 An on-chip pull-up resistor can be selected. <1> Specifies on-chip pull-up resistor in 1-bit units. <2> Does not specify on-chip pull-up resistor.
Data Sheet U14384EJ1V0DS
29
PD789304, 789306, 789314, 789316
10. OVERVIEW OF INSTRUCTION SET
This section lists the instruction set for the PD789304, 789306, 789314, and 789316. 10.1 Conventions 10.1.1 Operand expressions and description methods Operands are described in "Operand" column of each instruction in accordance with the description method of the instruction operand expression (see the assembler specifications for details). When there are two or more description methods, select one of them. Uppercase letters and symbols, #, !, $, and [ ] are key words and are described as they are. The meaning of each symbol is described below. * # : Immediate data specification * ! : Absolute address specification * $ : Relative address specification * [ ] : Indirect address specification
For immediate data, enter an appropriate numeric value or a label. When using a label, be sure to enter the #, !, $ and [ ] symbols. For operand register expressions, r and rp, either function names (X, A, C, etc.) or absolute names (names in parenthesis in the table below, R0, R1, R2, etc.) can be used for the description. Table 10-1. Operand Expressions and Description Methods
Expression r rp sfr saddr saddrp addr16 addr5 word byte bit Description Method X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7) AX (RP0), BC (RP1), DE (RP2), HL (RP3) Special function register symbol FE20H to FF1FH: immediate data or label FE20H to FF1FH: immediate data or label (even addresses only) 0000H to FFFFH: immediate data or label (even addresses only for 16-bit data transfer instruction) 0040H to 007FH: immediate data or label (even addresses only) 16-bit immediate data or label 8-bit immediate data or label 3-bit immediate data or label
30
Data Sheet U14384EJ1V0DS
PD789304, 789306, 789314, 789316
10.1.2 Description of "Operation" column A: X: B: C: D: E: H: L: AX: BC: DE: HL: PC: SP: PSW: CY: AC: Z: IE: NMIS: ( ): XH, XL: : : :
A register; 8-bit accumulator X register B register C register D register E register H register L register AX register pair; 16-bit accumulator BC register pair DE register pair HL register pair Program counter Stack pointer Program status word Carry flag Auxiliary carry flag Zero flag Interrupt request enable flag Flag indicating non-maskable interrupt servicing in progress Memory contents indicated by address or register contents in parenthesis Higher 8 bits and lower 8 bits of 16-bit register Logical product (AND) Logical sum (OR) Exclusive logical sum (exclusive OR) : Inverted data 16-bit immediate data or label Signed 8-bit data (displacement value)
addr16: jdisp8:
10.1.3 Description of "Flag" column (Blank): 0: 1: x: R: Unchanged Cleared to 0 Set to 1 Set/cleared according to the result Previously saved value is restored
Data Sheet U14384EJ1V0DS
31
PD789304, 789306, 789314, 789316
10.2 List of Operations
Mnemonic Operand Bytes Clocks Operation Z MOV r, #byte saddr, #byte sfr, #byte A, r r, A A, saddr saddr, A A, sfr sfr, A A, !addr16 !addr16, A PSW, #byte A, PSW PSW, A A, [DE] [DE], A A, [HL] [HL], A A, [HL + byte] [HL + byte], A XCH A, X A, r A, saddr A, sfr A, [DE] A, [HL] A, [HL + byte] MOVW rp, #word AX, saddrp saddrp, AX AX, rp rp, AX XCHW AX, rp
Note 3 Note 3 Note 3 Note 2 Note 1 Note 1
Flags AC CY
3 3 3 2 2 2 2 2 2 3 3 3 2 2 1 1 1 1 2 2 1 2 2 2 1 1 2 3 2 2 1 1 1
6 6 6 4 4 4 4 4 4 8 8 6 4 4 6 6 6 6 6 6 4 6 6 6 8 8 8 6 6 8 4 4 8
r byte (saddr) byte sfr byte Ar rA A (saddr) (saddr) A A sfr sfr A A (addr16) (addr16) A PSW byte A PSW PSW A A (DE) (DE) A A (HL) (HL) A A (HL + byte) (HL + byte) A AX Ar A (saddr) A (sfr) A (DE) A (HL) A (HL + byte) rp word AX (saddrp) (saddrp) AX AX rp rp AX AX rp x x x x x x
Notes 1. 2. 3. Remark
Except r = A Except r = A, X rp = BC, DE and HL only One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control register (PCC).
32
Data Sheet U14384EJ1V0DS
PD789304, 789306, 789314, 789316
Mnemonic Operand Bytes Clocks Operation Z ADD A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte] ADDC A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte] SUB A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte] SUBC A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte] AND A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte] 2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2 4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6 A, CY A + byte (saddr), CY (saddr) + byte A, CY A + r A, CY A + (saddr) A, CY A + (addr16) A, CY A + (HL) A, CY A + (HL + byte) A, CY A + byte + CY (saddr), CY (saddr) + byte + CY A, CY A + r + CY A, CY A + (saddr) + CY A, CY A + (addr16) + CY A, CY A + (HL) + CY A, CY A + (HL + byte) + CY A, CY A - byte (saddr), CY (saddr) - byte A, CY A - r A, CY A - (saddr) A, CY A - (addr16) A, CY A - (HL) A, CY A - (HL + byte) A, CY A - byte - CY (saddr), CY (saddr) - byte - CY A, CY A - r - CY A, CY A - (saddr) - CY A, CY A - (addr16) - CY A, CY A - (HL) - CY A, CY A - (HL + byte) - CY A A byte (saddr) (saddr) byte AAr A A (saddr) A A (addr16) A A (HL) A A (HL + byte) x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Flags AC CY x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x
Remark
One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control register (PCC).
Data Sheet U14384EJ1V0DS
33
PD789304, 789306, 789314, 789316
Mnemonic Operand Bytes Clocks Operation Z OR A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte] XOR A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte] CMP A, #byte saddr, #byte A, r A, saddr A, !addr16 A, [HL] A, [HL + byte] ADDW SUBW CMPW INC AX, #word AX, #word AX, #word r saddr DEC r saddr INCW DECW ROR ROL RORC ROLC rp rp A, 1 A, 1 A, 1 A, 1 2 3 2 2 3 1 2 2 3 2 2 3 1 2 2 3 2 2 3 1 2 3 3 3 2 2 2 2 1 1 1 1 1 1 4 6 4 4 8 6 6 4 6 4 4 8 6 6 4 6 4 4 8 6 6 6 6 6 4 4 4 4 4 4 2 2 2 2 A A byte (saddr) (saddr) byte AAr A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A A byte (saddr) (saddr) byte AAr A A (saddr) A A (addr16) A A (HL) A A (HL + byte) A - byte (saddr) - byte A-r A - (saddr) A - (addr16) A - (HL) A - (HL + byte) AX, CY AX + word AX, CY AX - word AX - word rr+1 (saddr) (saddr) + 1 rr-1 (saddr) (saddr) - 1 rp rp + 1 rp rp - 1 (CY, A7 A0, Am - 1 Am) x 1 time (CY, A0 A7, Am + 1 Am) x 1 time (CY A0, A7 CY, Am - 1 Am) x 1 time (CY A7, A0 CY, Am + 1 Am) x 1 time x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x x Flags AC CY
Remark
One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control register (PCC).
34
Data Sheet U14384EJ1V0DS
PD789304, 789306, 789314, 789316
Mnemonic Operand Bytes Clocks Operation Z SET1 saddr. bit sfr. bit A. bit PSW. bit [HL]. bit CLR1 saddr. bit sfr. bit A. bit PSW. bit [HL]. bit SET1 CLR1 NOT1 CALL CALLT CY CY CY !addr16 [addr5] 3 3 2 3 2 3 3 2 3 2 1 1 1 3 1 6 6 4 6 10 6 6 4 6 10 2 2 2 6 8 (saddr. bit) 1 sfr. bit 1 A. bit 1 PSW. bit 1 (HL). bit 1 (saddr. bit) 0 sfr. bit 0 A. bit 0 PSW. bit 0 (HL). bit 0 CY 1 CY 0 CY CY (SP - 1) (PC + 3)H, (SP - 2) (PC + 3)L, PC addr16, SP SP - 2 (SP - 1) (PC + 1)H, (SP - 2) (PC + 1)L, PCH (00000000, addr5 + 1), PCL (00000000, addr5), SP SP - 2 PCH (SP + 1), PCL (SP), SP SP + 2 PCH (SP + 1), PCL (SP), PSW (SP + 2), SP SP + 3, NMIS 0 (SP - 1) PSW, SP SP - 1 (SP - 1) rpH, (SP - 2) rpL, SP SP - 2 PSW (SP), SP SP + 1 rpH (SP + 1), rpL (SP), SP SP + 2 SP AX AX SP PC addr16 PC PC + 2 + jdisp8 PCH A, PCL X R RR R RR 1 0 x x x x x x x Flags AC CY
RET RETI
1 1
6 8
PUSH
PSW rp
1 1 1 1 2 2 3 2 1
2 4 4 6 8 6 6 6 6
POP
PSW rp
MOVW
SP, AX AX, SP
BR
!addr16 $addr16 AX
Remark
One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control register (PCC).
Data Sheet U14384EJ1V0DS
35
PD789304, 789306, 789314, 789316
Mnemonic Operand Bytes Clocks Operation Z BC BNC BZ BNZ BT $addr16 $addr16 $addr16 $addr16 saddr. bit, $addr16 sfr. bit, $addr16 A. bit, $addr16 PSW. bit, $addr16 BF saddr. bit, $addr16 sfr. bit, $addr16 A. bit, $addr16 PSW. bit, $addr16 DBNZ B, $addr16 C, $addr16 saddr, $addr16 NOP EI DI HALT STOP 2 2 2 2 4 4 3 4 4 4 3 4 2 2 3 1 3 3 1 1 6 6 6 6 10 10 8 10 10 10 8 10 6 6 8 2 6 6 2 2 PC PC + 2 + jdisp8 if CY = 1 PC PC + 2 + jdisp8 if CY = 0 PC PC + 2 + jdisp8 if Z = 1 PC PC + 2 + jdisp8 if Z = 0 PC PC + 4 + jdisp8 if (saddr. bit) = 1 PC PC + 4 + jdisp8 if sfr. bit = 1 PC PC + 3 + jdisp8 if A. bit = 1 PC PC + 4 + jdisp8 if PSW. bit = 1 PC PC + 4 + jdisp8 if (saddr. bit) = 0 PC PC + 4 + jdisp8 if sfr. bit = 0 PC PC + 3 + jdisp8 if A. bit = 0 PC PC + 4 + jdisp8 if PSW. bit = 0 B B - 1, then PC PC + 2 + jdisp8 if B 0 C C - 1, then PC PC + 2 + jdisp8 if C 0 (saddr) (saddr) - 1, then PC PC + 3 + jdisp8 if (saddr) 0 No Operation IE 1 (Enable Interrupt) IE 0 (Disable Interrupt) Set HALT Mode Set STOP Mode Flags AC CY
Remark
One instruction clock cycle is one CPU clock cycle (fCPU) selected via the processor clock control register (PCC).
36
Data Sheet U14384EJ1V0DS
PD789304, 789306, 789314, 789316
11. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
Parameter Power supply voltage Input voltage Symbol VDD VI1 VI2 P00 to P03, P10 to P13, P20 to P26, P30 to P33, X1 (CL1), X2 (CL2), XT1, XT2, RESET P50 to P53 N-ch open drain On-chip pull-up resistor Output voltage Output current, high VO IOH Per pin Total for all pins Output current, low IOL Per pin Total for all pins Operating ambient temperature Storage temperature TA Tstg Conditions Ratings -0.3 to +6.5 -0.3 to VDD + 0.3 -0.3 to +13 -0.3 to VDD + 0.3 -0.3 to VDD + 0.3 -10 -30 30 160 -40 to +85 -65 to +150
Note Note Note
Unit V V V V V mA mA mA mA C C
Note 6.5 V or less Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. Remarks 1. Pin names enclosed in parentheses are when using the PD789304, 789306. 2. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U14384EJ1V0DS
37
PD789304, 789306, 789314, 789316
Main System Clock Oscillator Characteristics Ceramic/crystal oscillation (PD789304, 789306) (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Resonator Ceramic resonator Recommended Circuit
IC X2 X1
1
Parameter Oscillation frequency (fX) Oscillation stabilization Note 2 time Oscillation frequency
Note 1 Note
Conditions
MIN. 1.0
TYP.
MAX. 5.0 4
Unit MHz ms
C2
C1
After VDD reaches oscillation voltage range MIN. 1.0 VDD = 4.5 to 5.5 V
Crystal resonator
IC
X2
X1
5.0 10 30
MHz ms ms
C2
C1
Oscillation stabilization Note 2 time
External clock
X2
X1
X1 input frequency (fX)
Note 1
1.0 85
5.0 500
MHz ns
X1 input high-/low-level width (tXH, tXL)
X2
X1
X1 input frequency (fX)
Note 1
VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V
1.0 85
5.0 500
MHz ns
X1 input high-/low-level width (tXH, tXL)
OPEN
Notes 1. 2.
Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Time required to stabilize oscillation after reset or STOP mode release. Use a resonator whose oscillation stabilizes within the oscillation stabilization wait time.
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figures to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
38
Data Sheet U14384EJ1V0DS
PD789304, 789306, 789314, 789316
RC oscillation (PD789314, 789316) (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Resonator RC resonator Recommended Circuit
CL1 CL2
Parameter Oscillation frequency Note 1 (fCC) Oscillation stabilization Note 2 time
Conditions
MIN. 2.0
TYP.
MAX. 4.0
Unit MHz
VDD = 2.7 to 5.5 V
32 128 1.0 100 4.0 500
s s
MHz ns
External clock
CL1
CL2
CL1 input frequency Note 1 (fCC) CL1 input high-/low-level width (tXH, tXL) CL1 input frequency Note 1 (fCC) CL1 input high-/low-level width (tXH, tXL) VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V
CL1
CL2
1.0 100
4.0 500
MHz ns
OPEN
Notes 1. 2.
Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Time required to stabilize oscillation after reset or STOP mode release.
Cautions 1. When using the main system clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. When the main system clock is stopped and the device is operating on the subsystem clock, wait until the oscillation stabilization time has been secured by the program before switching back to the main system clock.
Data Sheet U14384EJ1V0DS
39
PD789304, 789306, 789314, 789316
RC Oscillation Frequency Characteristics (TA = -40 to +85C)
Parameter Oscillation frequency Symbol fCC1 fCC2 fCC3 fCC4 fCC5 fCC6 fCC7 fCC8 fCC9 R = 4.7 k, C = 22 pF Target: 4 MHz R = 6.8 k, C = 22 pF Target: 3 MHz Conditions R = 11.0 k, C = 22 pF Target: 2 MHz VDD = 2.7 to 5.5 V VDD = 1.8 to 3.6 V VDD = 1.8 to 5.5 V VDD = 2.7 to 5.5 V VDD = 1.8 to 3.6 V VDD = 1.8 to 5.5 V VDD = 2.7 to 5.5 V VDD = 1.8 to 3.6 V VDD = 1.8 to 5.5 V MIN. 1.5 0.5 0.5 2.5 0.75 0.75 3.5 1.0 1.0 TYP. 2.0 2.0 2.0 3.0 3.0 3.0 4.0 4.0 4.0 MAX. 2.5 2.5 2.5 3.5 3.5 3.5 4.7 4.7 4.7 Unit MHz MHz MHz MHz MHz MHz MHz MHz MHz
Remarks 1. Set the RC to one of the above nine values so that the typical value of the oscillation frequency is within 2.0 to 4.0 MHz. 2. The resistor (R) and capacitor (C) error is not included.
40
Data Sheet U14384EJ1V0DS
PD789304, 789306, 789314, 789316
Subsystem Clock Oscillator Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Resonator Crystal resonator Recommended Circuit
IC XT1 XT2 R C3 C4
Parameter Oscillation frequency Note 1 (fXT) Oscillation stabilization Note 2 time XT1 input frequency Note 1 (fXT) XT1 input high-/low-level width (tXTH, tXTL)
Conditions
MIN. 32
TYP. 32.768 1.2
MAX. 35 2 10
Unit kHz s
VDD = 4.5 to 5.5 V
External clock
XT1
XT2
32 14.3
35 15.6
kHz
s
Notes 1. 2.
Indicates only oscillator characteristics. Refer to AC Characteristics for instruction execution time. Time required to stabilize oscillation after VDD reaches oscillation voltage range MIN.
Cautions 1. When using the subsystem clock oscillator, wire as follows in the area enclosed by the broken lines in the above figure to avoid an adverse effect from wiring capacitance. * Keep the wiring length as short as possible. * Do not cross the wiring with the other signal lines. * Do not route the wiring near a signal line through which a high fluctuating current flows. * Always make the ground point of the oscillator capacitor the same potential as VSS. * Do not ground the capacitor to a ground pattern through which a high current flows. * Do not fetch signals from the oscillator. 2. The subsystem clock oscillator is designed as a low-amplitude circuit for reducing current consumption, and is more prone to malfunction due to noise than the main system clock oscillator. Particular care is therefore required with the wiring method when the subsystem clock is used. Remark For the resonator selection and oscillator constant, customers are requested to either evaluate the oscillation themselves or apply to the resonator manufacturer for evaluation.
Data Sheet U14384EJ1V0DS
41
PD789304, 789306, 789314, 789316
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (1/4)
Parameter Output current, low Symbol IOL Per pin All pins Output current, high IOH Per pin All pins Input voltage, high VIH1 P10 to P13 VDD = 2.7 to 5.5 V 0.7VDD 0.9VDD VIH2 P50 to P53 N-ch open drain On-chip pullup resistor VIH3 RESET, P00 to P03, P20 to P26, P30 to P33 X1 (CL1), X2 (CL2), XT1, XT2 P10 to P13 VDD = 2.7 to 5.5 V 0.7VDD 0.9VDD VDD = 2.7 to 5.5 V 0.7VDD 0.9VDD VDD = 2.7 to 5.5 V 0.8VDD 0.9VDD VDD = 4.5 to 5.5 V VDD - 0.5 VDD - 0.1 VDD = 2.7 to 5.5 V 0 0 VIL2 P50 to P53 VDD = 2.7 to 5.5 V 0 0 VIL3 RESET, P00 to P03, P20 to P26, P30 to P33 X1 (CL1), X2 (CL2), XT1, XT2 VDD = 2.7 to 5.5 V 0 0 VDD = 4.5 to 5.5 V 0 0 VDD - 1.0 VDD - 0.5 1.0 0.5 1.0 0.4 Conditions MIN. TYP. MAX. 10 80 -1 -15 VDD VDD 12 12 VDD VDD VDD VDD VDD VDD 0.3VDD 0.1VDD 0.3VDD 0.1VDD 0.2VDD 0.1VDD 0.4 0.1 Unit mA mA mA mA V V V V V V V V V V V V V V V V V V V V V V V V
VIH4
Input voltage, low
VIL1
VIL4
Output voltage, high
VOH
VDD = 4.5 to 5.5 V, IOH = -1 mA VDD = 1.8 to 5.5 V, IOH = -100 A
Output voltage, low
VOL1
P00 to P03, P10 to P13, P20 to P26, P30 to P33
4.5 VDD 5.5 V, IOL = 10 mA 1.8 VDD < 4.5 V, IOL = 400 A
VOL2
P50 to P53
4.5 VDD < 5.5 V, IOL = 10 mA 1.8 VDD < 4.5 V, IOL = 1.6 mA
Remarks 1. Pin names enclosed in parentheses are when using the PD789314, 789316. 2. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
42
Data Sheet U14384EJ1V0DS
PD789304, 789306, 789314, 789316
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (2/4)
Parameter Input leakage current, high Symbol ILIH1 VIN = VDD Conditions P00 to P03, P10 to P13, P20 to P26, P30 to P33, RESET X1 (CL1), X2 (CL2), XT1, XT2 VIN = 12 V VIN = 0 V P50 to P53 (N-ch open drain) P00 to P03, P10 to P13, P20 to P26, P30 to P33, RESET X1 (CL1), X2 (CL2), XT1, XT2 P50 to P53 (N-ch open drain) VOUT = VDD VOUT = 0 V VIN = 0 V P00 to P03, P10 to P13, P20 to P26, P30 to P33 P50 to P53 50 100 MIN. TYP. MAX. 3 Unit
A
ILIH2 ILIH3 Input leakage current, low ILIL1
20 20 -3
A A A
ILIL2 ILIL3 Output leakage current, ILOH high Output leakage current, ILOL low Software pull-up resistor Mask option pull-up resistor R1
-20 -3
Note
A A A A
k
3 -3 200
R2
VIN = 0 V
10
30
60
k
Note If there is no on-chip pull-up resistor for P50 to P53 (specified by the mask option), if P50 to P53 have been set to input mode when a read instruction is executed to read from P50 to P53, a low-level input leakage current of up to -30 A flows during only one cycle. At all other times, the maximum leakage current is -3 A. Remarks 1. Pin names enclosed in parentheses are when using the PD789314, 789316. 2. Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U14384EJ1V0DS
43
PD789304, 789306, 789314, 789316
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (3/4)
Parameter Power supply Note 1 current (Ceramic/crystal oscillation) IDD2 Symbol IDD1 Conditions 5.0 MHz crystal oscillation operation mode (C1 = C2 = 22 pF) 5.0 MHz crystal oscillation HALT mode (C1 = C2 = 22 pF) 32.768 kHz crystal oscillation operation Note 4 mode (C3 = C4 = 22 pF, R1 = 220 k) IDD4 32.768 kHz crystal oscillation HALT Note 4 mode (C3 = C4 = 22 pF, R1 = 220 k) IDD5 STOP mode VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10%
Note 2 Note 3 Note 3
MIN.
TYP. 1.8 0.36 0.16 0.96 0.26 0.1 30 9 4
MAX. 2.9 0.9 0.45 1.92 0.76 0.34 58 26 12
Unit mA mA mA mA mA mA
Note 2 Note 3 Note 3
IDD3
A A A A A A A A A A A A
LCD VDD = 5.0 V 10% not VDD = 3.0 V 10% operating VDD = 2.0 V 10% LCD VDD = 5.0 V 10% operating VDD = 3.0 V 10% Note 5 VDD = 2.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10%
25 7 4 28 9.6 6 0.1 0.05 0.05
48 20 10 57 27.8 16 10 5.0 3.0
Note 6
Notes 1. 2. 3. 4. 5.
The port current (including the current that flows to the on-chip pull-up resistor) is not included. High-speed mode operation (when processor clock control register (PCC) is set to 00H) Low-speed mode operation (when PCC is set to 02H) When the main system clock is stopped This is the total current that flows when the LCD controller/driver is operating (LCDON0 = 1, VAON0 = 1, LIPS0 = 1). The power supply current when the LCD is not operating (LCDON0 = 0, VAON0 = 1, LIPS0 = 0) is included in IDD2.
6. Remark
This is the current when the LCD voltage booster circuit is stopped (LCDON0 = 0, VAON0 = 1). Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
44
Data Sheet U14384EJ1V0DS
PD789304, 789306, 789314, 789316
DC Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (4/4)
Parameter Power supply Note 1 current (RC oscillation) IDD2 Symbol IDD1 Conditions 4.0 MHz RC oscillation operation mode (R = 4.7 k, C = 22 pF) 4.0 MHz RC oscillation HALT mode (R = 4.7 k, C = 22 pF) 32.768 kHz crystal oscillation operation Note 4 mode (C3 = C4 = 22 pF, R1 = 220 k) IDD4 32.768 kHz crystal oscillation HALT Note 4 mode (C3 = C4 = 22 pF, R1 = 220 k) IDD5 STOP mode VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10%
Note 2 Note 3 Note 3 Note 2 Note 3 Note 3
MIN.
TYP. 1.65 0.65 0.38 1.1 0.6 0.35 30 9 4
MAX. 3.0 1.44 1.05 2.29 1.28 0.82 58 26 12
Unit mA mA mA mA mA mA
IDD3
A A A A A A A A A A A A
LCD VDD = 5.0 V 10% not VDD = 3.0 V 10% operating VDD = 2.0 V 10% LCD VDD = 5.0 V 10% operating VDD = 3.0 V 10% Note 5 VDD = 2.0 V 10% VDD = 5.0 V 10% VDD = 3.0 V 10% VDD = 2.0 V 10%
25 7 4 28 9.6 6 0.1 0.05 0.05
48 20 10 57 27.8 16 10 5.0 3.0
Note 6
Notes 1. 2. 3. 4. 5.
The port current (including the current that flows to the on-chip pull-up resistor) is not included. High-speed mode operation (when processor clock control register (PCC) is set to 00H) Low-speed mode operation (when PCC is set to 02H) When the main system clock is stopped This is the total current that flows when the LCD controller/driver is operating (LCDON0 = 1, VAON0 = 1, LIPS0 = 1). The power supply current when the LCD is not operating (LCDON0 = 0, VAON0 = 1, LIPS0 = 0) is included in IDD2.
6. Remark
This is the current when the LCD voltage booster circuit is stopped (LCDON0 = 0, VAON0 = 1). Unless specified otherwise, the characteristics of alternate-function pins are the same as those of port pins.
Data Sheet U14384EJ1V0DS
45
PD789304, 789306, 789314, 789316
AC Characteristics (1) Basic operation (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Cycle time (minimum instruction execution time) TMI40 input frequency Symbol TCY1 Conditions Operating with main system clock VDD = 2.7 to 5.5 V MIN. 0.4 1.6 114 0 0 TMI40 input high-/lowlevel width Interrupt input high/low-level width Key return input lowlevel width RESET low-level width tTIMH, tTIML tINTH, tINTL tKRL tRSL KR00 to KR03 10 10 INTP0 to INTP3 VDD = 2.7 to 5.5 V 0.1 1.8 10 122 TYP. MAX. 8.0 8.0 125 4 275 Unit
s s s
MHz kHz
Operating with subsystem clock fTMI VDD = 2.7 to 5.5 V
s s s
s s
TCY vs. VDD (main system clock)
60
20 10
Cycle time TCY [ s]
Guaranteed operation range 2.0 1.0 0.5 0.4
0.1 1 2 3 4 5 6 Power supply voltage VDD (V)
46
Data Sheet U14384EJ1V0DS
PD789304, 789306, 789314, 789316
(2) Serial interface 10, 20 (SIO10, SIO20) (TA = -40 to +85C, VDD = 1.8 to 5.5 V) (a) 3-wire serial I/O mode (internal clock output)
Parameter SCKn0 cycle time Symbol tKCY1 VDD = 2.7 to 5.5 V Conditions MIN. 800 3200 SCKn0 high-/low-level width SIn0 setup time (to SCKn0) SIn0 hold time (from SCKn0) Delay time from SCKn0 to SOn0 output tKH1, tKL1 tSIK1 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V
tKCY1/2-50 tKCY1/2-150
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns
150 500
tSI1
VDD = 2.7 to 5.5 V
400 600
tSO1
R = 1 k, C = 100 pF
Note
VDD = 2.7 to 5.5 V
0 0
250 1000
ns ns
Note R and C are the load resistance and load capacitance of the SOn0 output lines. Remark n = 1, 2
(b) 3-wire serial I/O mode (external clock input)
Parameter SCKn0 cycle time Symbol tKCY2 VDD = 2.7 to 5.5 V Conditions MIN. 800 3200 SCKn0 high-/low-level width SIn0 setup time (to SCKn0) SIn0 hold time (from SCKn0) Delay time from SCKn0 to SOn0 output tKH2, tKL2 tSIK2 VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V 400 1600 100 150 tSI2 VDD = 2.7 to 5.5 V 400 600 tSO2 R = 1 k, C = 100 pF
Note
TYP.
MAX.
Unit ns ns ns ns ns ns ns ns
VDD = 2.7 to 5.5 V
0 0
300 1000
ns ns
Note R and C are the load resistance and load capacitance of the SOn0 output lines. Remark n = 1, 2
Data Sheet U14384EJ1V0DS
47
PD789304, 789306, 789314, 789316
(c) UART mode (SIO20 only) (dedicated baud rate generator output)
Parameter Transfer rate Symbol VDD = 2.7 to 5.5 V Conditions MIN. TYP. MAX. 78125 19531 Unit bps bps
(d) UART mode (SIO20 only) (external clock input)
Parameter ASCK20 cycle time Symbol tKCY3 VDD = 2.7 to 5.5 V Conditions MIN. 800 3200 ASCK20 high-/lowlevel width Transfer rate tKH3, tKL3 VDD = 2.7 to 5.5 V 400 1600 VDD = 2.7 to 5.5 V 39063 9766 ASCK20 rise/fall time tR, tF 1 TYP. MAX. Unit ns ns ns ns bps bps
s
48
Data Sheet U14384EJ1V0DS
PD789304, 789306, 789314, 789316
AC Timing Test Points (excluding X1 (CL1) and XT1 inputs)
0.8VDD 0.2VDD 0.8VDD 0.2VDD
Test points
Clock Timing
1/fCLK tXL tXH VIH4 (MIN.) VIL4 (MAX.)
X1 (CL1) input
1/fXT tXTL tXTH VIH5 (MIN.) VIL5 (MAX.)
XT1 input
Remark
fCLK: fX or fCC
TMI Timing
1/fTMI tTIL tTIH
TMI40 input
Interrupt Input Timing
tINTL tINTH
INTP0 to INTP3
Key Return Input Timing
tKRL
KR00 to KR03
Data Sheet U14384EJ1V0DS
49
PD789304, 789306, 789314, 789316
RESET Input Timing
tRSL
RESET
Serial Transfer Timing 3-wire serial I/O mode:
tKCYm tKLm tKHm
SCKn0
tSIKm SIn0
tKSIm
Input data
tKSOm
SOn0
Output data
Remark
n, m = 1, 2
UART mode (external clock input):
tKCY3 tKL3 tR ASCK20 tKH3 tF
50
Data Sheet U14384EJ1V0DS
PD789304, 789306, 789314, 789316
LCD Characteristics (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter LCD output voltage variation range Doubler output Tripler output Voltage boost wait Note 1 time Symbol VLCD2 Conditions c1 to c4 = 0.47 F GAIN = 1 GAIN = 0 VLCD1 VLCD0 tVAWAIT c1 to c4 = 0.47 F c1 to c4 = 0.47 F GAIN = 0 GAIN = 1 5.0 VDD 5.5 V 4.5 VDD < 5.0 V 1.8 VDD < 4.5 V LCD output voltage Note 2 differential (common) LCD output voltage Note 2 (segment) differential VODC VODS IO = 5 A IO = 1 A MIN. 0.84 1.26 2VLCD2 - 0.1 3VLCD2 - 0.15 0.5 2.0 1.0 0.5 0 0 0.2 0.2 TYP. 1.0 1.5 2.0VLCD2 3.0VLCD2 MAX. 1.165 1.74 2.0VLCD2 3.0VLCD2 Unit V V V V s s s s V V
Notes 1. 2.
This is the wait time from when voltage boosting is started (VAON0 = 1) until display is enabled (LCDON0 = 0). The voltage differential is the difference between the segment and common signal output's actual and ideal output voltages.
Remark
c1: Capacitor connected between CAPH and CAPL c2: Capacitor connected between VLC0 and ground c3: Capacitor connected between VLC1 and ground c4: Capacitor connected between VLC2 and ground
Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = -40 to +85C)
Parameter Data retention power supply voltage Release signal set time Symbol VDDDR tSREL Conditions MIN. 1.8 0 TYP. MAX. 5.5 Unit V
s
Data Sheet U14384EJ1V0DS
51
PD789304, 789306, 789314, 789316
Data Retention Timing
Internal reset operation HALT mode STOP mode Data retention mode Operation mode
VDD
VDDDR STOP instruction execution
tSREL
RESET
tWAIT
HALT mode STOP mode Data retention mode Operation mode
VDD
VDDDR STOP instruction execution
tSREL
Standby release signal (interrupt request) tWAIT
52
Data Sheet U14384EJ1V0DS
PD789304, 789306, 789314, 789316
Oscillation Stabilization Wait Time (TA = -40 to +85C, VDD = 1.8 to 5.5 V)
Parameter Oscillation stabilization wait Note 1 time (ceramic/crystal oscillation) Oscillation stabilization wait time (RC oscillation) tWAIT Symbol tWAIT Conditions Release by RESET Release by interrupt Release by RESET Release by interrupt MIN. TYP. 2 /fX Note 2 2 /fCC 2 /fCC
7 7 15
MAX.
Unit s s s s
Notes 1. 2.
Use a resonator whose oscillation stabilizes within the oscillation stabilization wait time. Selection of 2 /fX, 2 /fX, or 2 /fX is possible with bits 0 to 2 (OSTS0 to OSTS2) of the oscillation stabilization time select register (OSTS).
12 15 17
Remarks 1. fX: Main system clock oscillation frequency (ceramic/crystal oscillation) 2. fCC: Main system clock oscillation frequency (RC oscillation)
Data Sheet U14384EJ1V0DS
53
PD789304, 789306, 789314, 789316
12. CHARACTERISTICS CURVES OF LCD CONTROLLER/DRIVER (REFERENCE VALUES)
(1) Characteristics curves of voltage boost stabilization time The following shows the characteristics curves of the time from the start of voltage boost (VAON0 = 1) and the changes in the LCD output voltage (when GAIN is set to 1 (using the 3 V display panel))
LCD Output Voltage/Voltage Boost Time 5.5 5 4.5 4 VDD = 4.5 V VDD = 5 V VDD = 5.5 V
LCD output voltage [V]
3.5 VLCD0 3 2.5 VLCD1 2 1.5 VLCD2 1 0.5 0 0 500 1000 1500 2000 Voltage boost time [ms] 2500 3000 3500 4000
54
Data Sheet U14384EJ1V0DS
PD789304, 789306, 789314, 789316
(2) Temperature characteristics of LCD output voltage The following shows the temperature characteristics curves of LCD output voltage.
LCD Output Voltage/Temperature (When GAIN = 1)
5
VLCD2
VLCD1
VLCD0
4
LCD output voltage [V]
3
2
1
0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [C]
LCD Output Voltage/Temperature (When GAIN = 0)
5
VLCD2
VLCD1
VLCD0
4
LCD output voltage [V]
3
2
1
0 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Temperature [C]
Data Sheet U14384EJ1V0DS
55
PD789304, 789306, 789314, 789316
13. PACKAGE DRAWINGS
64-PIN PLASTIC QFP (14x14)
A B
48 49
33 32
detail of lead end S CD Q R
64 1
17 16
F G H I
M
J
P
K S
N
S
L M
NOTE Each lead centerline is located within 0.15 mm of its true position (T.P.) at maximum material condition.
ITEM A B C D F G H I J K L M N P Q R S
MILLIMETERS 17.60.4 14.00.2 14.00.2 17.60.4 1.0 1.0 0.37 +0.08 -0.07 0.15 0.8 (T.P.) 1.80.2 0.80.2 0.17 +0.08 -0.07 0.10 2.550.1 0.10.1 55 2.85 MAX. P64GC-80-AB8-5
56
Data Sheet U14384EJ1V0DS
PD789304, 789306, 789314, 789316
64-PIN PLASTIC TQFP (12x12)
A B
48 49
33 32 S P
detail of lead end
T C D R
L U
64 1 F G H I
M
17 16
Q
J
ITEM A B MILLIMETERS 14.00.2 12.00.2 12.00.2 14.00.2 1.125 1.125 0.32 +0.06 -0.10 0.13 0.65 (T.P.) 1.00.2 0.5 0.17 +0.03 -0.07 0.10 1.0 0.10.05 3 +4 -3 1.10.1 0.25 0.60.15 P64GK-65-9ET-2
K S M N
NOTE
Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition.
C D F G H I J K L M N P Q R S T U
S
Data Sheet U14384EJ1V0DS
57
PD789304, 789306, 789314, 789316
14. RECOMMENDED SOLDERING CONDITIONS
The PD789304, 789306, 789314, and PD789316 should be soldered and mounted under the following recommended conditions. For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting Technology Manual (C10535E). For soldering methods and conditions other than those recommended below, contact an NEC sales representative. Table 14-1. Surface Mounting Type Soldering Conditions xxx-AB8: 64-pin plastic QFP (14 x 14) xxx PD789304GC-xxx xxx-AB8: 64-pin plastic QFP (14 x 14) xxx PD789306GC-xxx xxx-AB8: 64-pin plastic QFP (14 x 14) xxx PD789314GC-xxx xxx-AB8: 64-pin plastic QFP (14 x 14) xxx PD789316GC-xxx
Soldering Method Infrared reflow VPS Wave soldering Partial heating Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: three times or less Package peak temperature: 215C, Time: 40 seconds max. (at 200C or higher), Count: three times or less Solder bath temperature: 260C max., Time: 10 seconds max., Count: Once, Preheating temperature: 120C max. (package surface temperature) Pin temperature: 300C max. Time: 3 seconds max. (per pin row) Recommended Condition Symbol IR35-00-3 VP15-00-3 WS60-00-1 --
Caution Do not use different soldering method together (except for partial heating). xxx-9ET: 64-pin plastic TQFP (fine pitch) (12 x 12) xxx PD789304GK-xxx xxx-9ET: 64-pin plastic TQFP (fine pitch) (12 x 12) xxx PD789306GK-xxx xxx-9ET: 64-pin plastic TQFP (fine pitch) (12 x 12) xxx PD789314GK-xxx xxx-9ET: 64-pin plastic TQFP (fine pitch) (12 x 12) xxx PD789316GK-xxx
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (at 210C or Note higher), Count: two times or less, Exposure limit: 7 days (after that, prebake at 125C for 10 hours) Package peak temperature: 215C, Time: 40 seconds max. (at 200C or Note (after that, higher), Count: two times or less, Exposure limit: 7 days prebake at 125C for 10 hours) Pin temperature: 300C max. Time: 3 seconds max. (per pin row) Recommended Condition Symbol IR35-107-2
VPS
VP15-107-2
Partial heating
--
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period. Caution Do not use different soldering method together (except for partial heating).
58
Data Sheet U14384EJ1V0DS
PD789304, 789306, 789314, 789316
APPENDIX A. DEVELOPMENT TOOLS
The following development tools are available for system development using the PD789304, 789306, 789314, and 789316. Language Processing Software
RA78K0S
Notes 1, 2, 3 Notes 1, 2, 3 Notes 1, 2, 3 Notes 1, 2, 3
Assembler package common to 78K/0S Series C compiler package common to 78K/0S Series Device file for PD789306, 789316 Subseries C compiler library source file common to 78K/0S Series
CC78K0S
DF789306
CC78K0S-L
Flash Memory Writing Tools
Flashpro III Note 4 (Part No. FL-PR3 , PG-FP3) FA-64GC FA-64GK
Note 4
Flash programmer dedicated to on-chip flash memory microcontroller Flash memory writing adapter for 64-pin plastic QFP (GC-AB8 type) Flash memory writing adapter for 64-pin plastic TQFP (fine pitch) (GK-9ET type)
Note 4
Debugging Tools
IE-78K0S-NS In-circuit emulator IE-70000-MC-PS-B AC adapter IE-70000-98-IF-C Interface adapter IE-70000-CD-IF-A PC card interface IE-70000-PC-IF-C Interface adapter IE-70000-PCI-IF-A Interface adapter IE-789306-NS-EM1 Emulation board NP-64GC NP-64GK
Note 4
This is an in-circuit emulator for debugging hardware and software of application system using the 78K/0S Series. It supports the integrated debugger (ID78K0S-NS). It is used with an AC adapter, emulation probe, and interface adapter for connecting the host machine. This is the adapter for supplying power from an AC-100 to 240 V outlet. This adapter is needed when PC-9800 series PC (except notebook type) is used as the host machine for an IE-78K0S-NS (supports C bus). This PC card and interface cable are needed when a PC-9800 series notebook-type PC is used as the host machine for an IE-78K0S-NS (supports PCMCIA socket). This adapter is needed when an IBM PC/ATTM or compatible PC is used as the host machine for an IE-78K0S-NS (supports ISA bus). This adapter is needed when a PC that includes a PCI bus is used as the host machine for an IE-78K0S-NS. This is an emulation board for emulating the peripheral hardware inherent to the device. It is used with an in-circuit emulator. This is a board that is used to connect an in-circuit emulator to the target system. It is for 64-pin plastic QFP (GC-AB8 type). This is a board that is used to connect an in-circuit emulator to the target system. It is for 64-pin plastic TQFP (GK-9ET type). System simulator common to 78K/0S Series Integrated debugger common to 78K/0S Series Device file for PD789306, 789316 Subseries
Note 4
SM78K0S
Notes 1, 2 Notes 1, 2
ID78K0S-NS DF789306
Notes 1, 2
Real-Time OS
MX78K0S
Notes 1, 2
OS for 78K/0S Series
Data Sheet U14384EJ1V0DS
59
PD789304, 789306, 789314, 789316
Notes 1. 2. 3. 4. Remark Based on PC-9800 series (Japanese Windows) Based on IBM PC/AT compatible (Japanese/English Windows) Based on HP9000 series 700TM (HP-UXTM), SPARCstationTM (SunOSTM, SolarisTM), or NEWSTM (NEWS-OSTM) This product is manufactured by Naito Densei Machida Mfg. Co., Ltd. (TEL +81-44-822-3813). The RA78K0S, CC78K0S, and SM78K0S are used in combination with the DF789306.
60
Data Sheet U14384EJ1V0DS
PD789304, 789306, 789314, 789316
APPENDIX B. RELATED DOCUMENTS
Documents Related to Devices
Document Name Document No. This manual To be prepared U14800E U11047E
PD789304, 789306, 789314, 789316 Data Sheet PD78F9306, 78F9316 Data Sheet PD789306, 789316 Subseries User's Manual
78K/0S Series User's Manual Instructions
Documents Related to Development Tools (User's Manuals)
Document Name RA78K0S Assembler Package Operation Language Structured Assembly Language CC78K0S C Compiler Operation Language SM78K0S, SM78K0 System Simulator Ver. 2.10 or Later Windows Based SM78K Series System Simulator Ver. 2.10 or Later ID-78K0-NS, ID78K0S-NS Integrated Debugger Ver. 2.20 or Later Windows Based IE-78K0S-NS In-Circuit Emulator IE-789306-NS-EM1 Emulation Board Operation External Part User Open Interface Specifications Operation Document No. U11622E U11599E U11623E U11816E U11817E U14611E U15006E U14910E U13549E To be prepared
Documents Related to Embedded Software (User's Manual)
Document Name 78K/0S Series OS MX78K0S Fundamental Document No. U12938E
Other Related Documents
Document Name SEMICONDUCTOR SELECTION GUIDE Products & Packages (CD-ROM) Semiconductor Device Mounting Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semiconductor Device Reliability/Quality Control System Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD) Document No. X13769X C10535E C11531E C10983E C11892E
Caution The related documents listed above are subject to change without notice. Be sure to use the latest version of each document for designing.
Data Sheet U14384EJ1V0DS
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PD789304, 789306, 789314, 789316
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
EEPROM is a trademark of NEC Corporation. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. PC/AT is a trademark of International Business Machines Corporation. HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc. Solaris and SunOS are trademarks of Sun Microsystems, Inc. NEWS and NEWS-OS are trademarks of Sony Corporation.
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Data Sheet U14384EJ1V0DS
PD789304, 789306, 789314, 789316
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC product in your application, pIease contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:
* * * * *
Device availability Ordering information Product release schedule Availability of related technical literature Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth) Network requirements
*
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California Tel: 408-588-6000 800-366-9782 Fax: 408-588-6130 800-729-9288
NEC Electronics (Germany) GmbH
Benelux Office Eindhoven, The Netherlands Tel: 040-2445845 Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
NEC Electronics Hong Kong Ltd. NEC Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-3067-5800 Fax: 01-3067-5899 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
NEC Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 03 02 Fax: 0211-65 03 490
NEC Electronics (France) S.A. NEC Electronics (UK) Ltd.
Milton Keynes, UK Tel: 01908-691-133 Fax: 01908-670-290 Madrid Office Madrid, Spain Tel: 091-504-2787 Fax: 091-504-2860
NEC Electronics Singapore Pte. Ltd.
Novena Square, Singapore Tel: 253-8311 Fax: 250-3583
NEC Electronics Taiwan Ltd. NEC Electronics Italiana s.r.l.
Milano, Italy Tel: 02-66 75 41 Fax: 02-66 75 42 99
NEC Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 80 820 Fax: 08-63 80 388
Taipei, Taiwan Tel: 02-2719-2377 Fax: 02-2719-5951
NEC do Brasil S.A.
Electron Devices Division Guarulhos-SP, Brasil Tel: 11-6462-6810 Fax: 11-6462-6829
J01.2
Data Sheet U14384EJ1V0DS
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